A technology for designing a semiconductor device, which has been discussed by the present inventors, is related to a semiconductor device having at least one substrate bias circuit configured according to design data. There may be cases in which, while a circuit cell kept at a low threshold voltage exists in circuit cells of a semiconductor device to improve the operating speed, for example, a problem relating to leakage current arises due to such a reduction in threshold voltage, thereby leading to an increase in power consumption and a thermal runaway during testing.
A substrate bias circuit is a circuit in which, when it is desired to suppress the leakage current in the circuit cell, a predetermined voltage is applied to a well in which the circuit cell is placed, thereby to increase the threshold voltage of the circuit cell, so as to suppress the leakage current; whereas, when the circuit cell is operated at high speed, the supply of voltage to the well is stopped, and the threshold voltage is lowered again, thereby realizing high-speed operation. A specific example of a substrate bias circuit of a semiconductor device having a CMOS circuit will be considered. In this example, there is a first well, in which one transistor constituting the CMOS circuit is disposed, and a first power supply on the high potential side are connected to each other via a first switch transistor; whereas, a second well, in which the other transistor constituting the CMOS circuit is disposed, and a second power supply on the reference potential side are connected to each other via a second switch transistor. Upon testing the semiconductor device having such a configuration, the first and second switch transistors are turned off and a potential suitable for testing is supplied from the outside to thereby suppress thermal runaway caused by the leakage current. On the other hand, during the normal operation of the semiconductor device, the first and second transistors are turned off and the first and second wells are respectively connected to the first and second power supplies to thereby prevent variations in operating speed and a latch-up or the like. For example, see Japanese Unexamined Patent Application No. Hei 9(1997)-521146 (Application number of the priority: Japanese Unexamined Patent Application No. Hei 7(1995)-315459, and International publication Number: PCT/WO97/21247, pp. 15–20, FIGS. 1 to 5).